VHDL and Verilog
VHDL or VHSIC Hardware Description Language, is commonly used as a design-entry language for FPGA s in electronic design automation.
Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International .
wishbone bus and ["PCI2Whishbone"-Bridge].
HDL (hardware description languages) modules, when distributed, are called "cores".