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Hardware

VHDL and Verilog

VHDL or VHSIC Hardware Description Language, is commonly used as a design-entry language for FPGA s in electronic design automation.

A VHDL simulator called GHDL (homepage||package) is included in Debian. It can save waveforms generated by a VHDL model in VCD (Value Change Dump) format, which can be viewed using Gtkwave (package).

Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International .

• http://en.wikipedia.org/wiki/VHDL

• http://www.angelfire.com/in/rajesh52/verilogvhdl.html

• http://www.accellera.org/home

• wishbone bus and ["PCI2Whishbone"-Bridge].

• Altera.

• Blowfish.

• HDL (hardware description languages) modules, when distributed, are called "cores".

• wiki:Self:VHDL A free blowfish core written in.

• LVDS