VHDL and Verilog

VHDL or VHSIC Hardware Description Language, is commonly used as a design-entry language for FPGA s in electronic design automation.

A VHDL simulator called GHDL (homepage||package) is included in Debian. It can save waveforms generated by a VHDL model in VCD (Value Change Dump) format, which can be viewed using Gtkwave (package).

Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International .