This page contains details about the port of Debian for the RISC-V architecture (riscv64).

In a nutshell

What is RISC-V?

From the Wikipedia entry for RISC-V:

RISC-V (pronounced "risk-five") is an open source instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles.

In contrast to most ISAs, RISC-V is freely available for all types of use, permitting anyone to design, manufacture and sell RISC-V chips and software. While not the first open ISA, it is significant because it is designed to be useful in modern computerized devices such as warehouse-scale cloud computers, high-end mobile phones and the smallest embedded systems. Such uses demand that the designers consider both performance and power efficiency. The instruction set also has a substantial body of supporting software, which fixes the usual weakness of new instruction sets.

The project was originated in 2010 by researchers in the Computer Science Division at UC Berkeley, but many contributors are volunteers and industry workers that are unaffiliated with the university.

There are different versions of the instruction set for 32, 64 and 128 bits; operating as little-endian by default.

What is a Debian port?

In short, a port in Debian terminology means to provide the software normally available in the Debian archive (over 20,000 source packages) ready to install and run on systems based in a given computer architecture with the Linux kernel, or kernel-architecture combinations, with other kernels including Hurd and FreeBSD.

See and DebianPorts for more information.

What are the goals of this project in particular?

In this project the goal is to have Debian ready to install and run in systems implementing variants of the RISC-V ISA:

The ISA variant is the "default flavour" recommended by the designers, and the one that seems to attract more interest for planned implementations that might become available in the next few years (development boards, possible consumer hardware or servers).

While 32-bit and 128-bit implementations are possible, there are problems with this:

Upstream project / Architecture / Hardware

Upstream project / Community

Architecture details


There are different efforts from organisations around the world (research institutes, commercial companies, ...) that have shown interest in this project. Perhaps they will create some hardware available for purchase in the future, but there is nothing available or announced at this time.

The most interesting/promising project in this respect is the lowRISC project:

lowRISC is a not-for-profit organisation working closely with the University of Cambridge and the open-source community.
lowRISC is creating a fully open-sourced, Linux-capable, RISC-V-based SoC, that can be used either directly or as the basis for a custom design. [...]
Our open-source SoC (System-on-a-Chip) designs will be based on the 64-bit RISC-V instruction set architecture. Volume silicon manufacture is planned as is a low-cost development board. [...]

FPGA implementations

There are cores freely available such as Rocket, implementing the 64-bit scalar flavour of the RISC-V ISA (and MMU and an optional IEEE 754-2008-compliant FPU), which can be synthetised to an FPGA.

Debian port information

Current Status

The binutils support for RISC-V has been accepted upstream in November/December 2016 and will be part of binutils 2.28 (expected to be released in Q1/2017).

The gcc support for RISC-V has been accepted for upstream inclusion by the GCC Steering Committee but is still pending the final stages of the technical review as there have been a number of review comments that need to be addressed in a new version of the upstreaming patchset. There is reason for hoping that the RISC-V support could make it into the GCC 7 release, but this depends on how fast the review process can be finished.

The preparations for this port started in private a while ago, but nothing has been made public so far and nothing useful yet for users and developers.

The main reason is the lack of official support for this architecture in fundamental pieces of the toolchain (binutils, gcc, glibc), the main OS kernel (linux) or even other software that might help with the port (e.g. qemu). All of the mentioned pieces have support in progress and are considered to submit for upstreaming, but nothing definitive has happened at the moment.

In particular, a recent message informed about some upcoming changes to the supervisor specifications (the ABI), which will affect binutils at least. Starting a Debian port without the ISA being settled is not very good, since the effort will need to be restarted from scratch.

It is expected that this situation will change soon (within few months) and that progress on this port can be started.



Hardware Sponsors:


Created page of the port in the wiki

APT sources.list

Follow instructions in: . Example:

 deb sid main
 deb unreleased main
 deb-src sid main

Mirrors (use them if possible, they may be closer to you):

buildd (build-daemon) information


Currently there are no porterboxes available. See the qemu section to install locally, if available.


qemu emulation is not possible yet since the changes are not upstreamed, and the code is still being revised for changes in the specifications.

In the future, when qemu works it sould be possible to do something like:

Cross compilation

When support for RISC-V targets are added to gcc upstream and enabled in the relevant packages in Debian, they can be installed directly from the main Debian repositories:

  # apt install gcc-riscv64-linux-gnu g++-riscv64-linux-gnu


Mailing list


Bugs (BTS)

Subject: foo: FTBFS on riscv64

Package: foo
Version: 1.2.3-4
Usertags: riscv64

The version of the package currently FBTFS on the riscv64 port:



Subject: riscv64 usertags for #BUGNUMBER

usertag BUGNUMBER + riscv64


Subject: Setting riscv64 usertags

Control: user
Control: usertag -1 + riscv64