Current status

Patch for GCC PR44364 has resolved all known floating-point issues to date!!!

Current 'powerpcspe' bug list

http://bugs.debian.org/cgi-bin/pkgreport.cgi?tag=powerpcspe;users=debian-powerpcspe@breakpoint.cc

Repositories and Build Status

Hosting for the unofficial PowerPCSPE port is graciously provided by the wonderful people at debian-ports.org. In particular we'd like to thank Aurelien Jarno for his help getting everything set up.

Latest Statistics

Packages which need fixes to build natively (List is incomplete)

Package

Assigned-to

Status

Debian Bug

Comments

dpkg

Kyle Moffett

Merged

#575158

eglibc

Kyle Moffett

Merged

#579778

gcc-4.3

TODO

gcc-4.4

Kyle Moffett

Merged/Buggy

#579780

gcc-4.5

N/A

Merged/Buggy

#579780

libffi

Kyle Moffett

Patched

Upstream soft-float ABI support is buggy

lintian

Sebastian

Submitted

#581314

openjdk-6

Sebastian

Needs some testing

openoffice

Sebastian

Need build test

openssl

Kyle Moffett

Submitted

#579805

strace

Sebastian

Submitted

#579842

xorg

Sebastian

Submitted

#583288

xulrunner

Sebastian

Submitted

#586072

Packages for which fixes have been merged

Package

Version

VCS Commit

Comment

eglibc

2.10.2-9

FIXME

Upstream still needs various fixes

gcc-4.4

4.4.4-2

FIXME

Upstream still needs various fixes

gcc-4.5

4.5.0-3

FIXME

Upstream still needs various fixes

Architecture summary

The 'powerpcspe' architecture is a binary-incompatible variant of the PowerPC/POWER designed and supported by FreeScale and IBM. It is also known under the trade names "e500"/"MPC8500" and "e200"/"MPC5xx".

Additional information can be found at:

Instruction set

In particular, the 'powerpcspe' architecture lacks the classic FPU with dedicated FPRs found on most other PowerPC systems. It is replaced with a set of "SPE" instructions which perform floating-point operations on the integer registers.

In an unfortunate choice of architecture design, the instructions used for the "SPE" operations overlap with those for the Altivec unit on most other modern PowerPC cores.

Chipset details

The "e500v2"-series chips have 64-bit GPRs, where the high 32-bits are accessible only via the special "SPE" instructions, allowing them to make efficient use of the "double" datatype.

The relatively rare "e500v1"-series chips have only 32-bit GPRs, and require software traps and emulation to support native "double".

The "e200z3" and "e200z6" chips have no support for floating point at all, but with software traps and emulation are binary-compatible with the "e500"-series chips.

GCC/EGLIBC considerations

The Debian port to this architecture specifically chooses to optimize for the higher-end chips (e500v2), as most of the others are targeted at automotive applications or no longer in production.

GCC 4.4.4+ currently suffer from PR44169, causing most code using Thread Local Storage to be miscompiled and crash when built with -O1. The problem does not exist in GCC 4.4.3 or older. UPDATE: This has been fixed in 4_4-branch, 4_5-branch, and trunk

Some versions of GCC also seems to suffer from PR44364 in which the upper half of the 64-bit GPRs (used by floating point and vector code) does not always get saved on the stack before being overwritten. This bug has been confirmed and a patch is available. The patch seems to fix all known issues to date.

Full support for the e500v2 requires the following options to GCC's "configure":

Please note that the  --with-long-double-128  is desired to match the behavior of long double on other PowerPC-based platforms. (Otherwise long double is exactly the same as double).

Final notes

At this time the 'powerpcspe' architecture port is still very much an unofficial port. While we hope that will change in the future, it is entirely possible that the embedded niche of the processor will make such an official Debian port problematic.