In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates.

Probably the best tool in Debian for synthesis is yosys. It accepts an RTL description of a digital circuit and transforms this into a netlist of digital standard cells. It also has some support for making a netlist with LUTs which are needed for FPGA design. yosys uses berkeley-abc for parts of the logic optimization.

In order to create a physical layout of the digital netlist, there is a need for a placement tool and a routing tool. In Debian, there is currently only a routing tool, qrouter. A tool called graywolf ( which can be used for placement will hopefully be packaged for Debian soon. For information about how all these tools can be used together, take a look at qflow (, which also hopefully will be packaged for Debian soon..

See also