Tool chain for Lattice iCE40 FPGAs
There is now a complete open source tool chain for some FPGAs from Lattice Semiconductor. The tool chain consists of the following tools:
- yosys - for logic synthesis of Verilog code. the output is a netlist describing how all cells are connected together in BLIF format.
- arachne-pnr (NEW queue) - for placement and routing of the netlist. the output is a textual bitstream
- fpga-icestorm - for preparing the bitstream for the FPGA, and transferring it to the FPGA using libusb/libftdi
It currently supports two FPGAs:
- Lattice Semiconductor iCE40LP/HX1K
- Lattice Semiconductor iCE40LP/HX8K
There are quite affordable evaluation kits for these two FPGAs called "iCEstick Evaluation Kit" and "iCE40-HX8K Breakout Board".
To get a Verilog code file called mydesign.v to "run" on an FPGA, the following commands are needed:
- yosys -q -p "synth_ice40 -blif mydesign.blif" mydesign.blif
- arachne-pnr -p mydesign.pcf mydesign.blif -o mydesign.txt
- icepack mydesign.txt mydesign.bin
- iceprog mydesign.bin
The .pcf file is a file containing the mapping between pin numbers and ports of the Verilog module. It consist of multiple lines of "set_io D1 99", where D1 in this case is an input or output of the Verilog module called "D1", and 99 is the pin number of the Lattice FPGA.