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=== Example files ===

Example .pcf-file (which works with HX1K):
{{{
set_io D1 99
set_io D2 98
set_io D3 97
set_io D4 96
set_io D5 95
set_io clk 21
}}}


Example verilog (.v) file:
{{{#!highlight verilog
module top(input clk, output D1, output D2, output D3, output D4, output D5);
   
   reg ready = 0;
   reg [23:0] divider;
   reg [3:0] rot;
   
   always @(posedge clk) begin
      if (ready)
    begin
       if (divider == 12000000)
         begin
        divider <= 0;
        rot <= {rot[2:0], rot[3]};
         end
       else
         divider <= divider + 1;
    end
      else
    begin
       ready <= 1;
       rot <= 4'b0001;
       divider <= 0;
    end
   end
   
   assign D1 = rot[0];
   assign D2 = rot[1];
   assign D3 = rot[2];
   assign D4 = rot[3];
   assign D5 = 1;
endmodule
}}}

Tool chain for Lattice iCE40 FPGAs

There is now a complete open source tool chain for some FPGAs from Lattice Semiconductor. The tool chain consists of the following tools:

  • yosys - for logic synthesis of Verilog code. the output is a netlist describing how all cells are connected together in BLIF format.

  • arachne-pnr (NEW queue) - for placement and routing of the netlist. the output is a textual bitstream

  • fpga-icestorm - for preparing the bitstream for the FPGA, and transferring it to the FPGA using libusb/libftdi

It currently supports two FPGAs:

  • Lattice Semiconductor iCE40LP/HX1K
  • Lattice Semiconductor iCE40LP/HX8K

There are quite affordable evaluation kits for these two FPGAs called "iCEstick Evaluation Kit" and "iCE40-HX8K Breakout Board".

To get a Verilog code file called mydesign.v to "run" on an FPGA, the following commands are needed:

  • yosys -q -p "synth_ice40 -blif mydesign.blif" mydesign.v
  • arachne-pnr -p mydesign.pcf mydesign.blif -o mydesign.txt
  • icepack mydesign.txt mydesign.bin
  • iceprog mydesign.bin

The .pcf file is a file containing the mapping between pin numbers and ports of the Verilog module. It consist of multiple lines of "set_io D1 99", where D1 in this case is an input or output of the Verilog module called "D1", and 99 is the pin number of the Lattice FPGA.

Example files

Example .pcf-file (which works with HX1K):

set_io D1 99
set_io D2 98
set_io D3 97
set_io D4 96
set_io D5 95
set_io clk 21

Example verilog (.v) file:

   1 module top(input clk, output D1, output D2, output D3, output D4, output D5);
   2    
   3    reg ready = 0;
   4    reg [23:0]     divider;
   5    reg [3:0]      rot;
   6    
   7    always @(posedge clk) begin
   8       if (ready) 
   9     begin
  10        if (divider == 12000000) 
  11          begin
  12         divider <= 0;
  13         rot <= {rot[2:0], rot[3]};
  14          end
  15        else 
  16          divider <= divider + 1;
  17     end 
  18       else 
  19     begin
  20        ready <= 1;
  21        rot <= 4'b0001;
  22        divider <= 0;
  23     end 
  24    end 
  25    
  26    assign D1 = rot[0];
  27    assign D2 = rot[1];
  28    assign D3 = rot[2];
  29    assign D4 = rot[3];
  30    assign D5 = 1;
  31 endmodule