Tool chain for Lattice iCE40 FPGAs

Hardware to buy

There is now a complete Open Source tool chain for some FPGAs from Lattice Semiconductor. For a convincing video that these devices and the Open Source development tools are useful, see:

The pipeline employs the following tools:

The final step, i.e. preparing the bitstream for the FPGA, and transferring it to the FPGA, uses:

This pipeline of yosys, arachne-pnr and icestorm now supports two FPGAs, as presented below. Another overview is found on this icoboard page.


To get a Verilog code file called mydesign.v to "run" on an FPGA, the following commands are needed. Yosys needs a Verilog (.v) file as input (example shown below) and arachne-pnr also needs the Physical Constraints file (.pcf) file to link ports in the Verilog file with ports on the hardware:

   yosys -q -p "synth_ice40 -blif mydesign.blif" mydesign.v \
&& arachne-pnr -p mydesign.pcf mydesign.blif -o mydesign.txt \
&& icepack mydesign.txt mydesign.bin \
&& iceprog mydesign.bin

For the CAT-Board, instead of using iceprog use litterbox. This is nicely described on .

The Debian packages of this Open Source tool chain were successfully tested with the iCEstick Evaluation Kit (iCE40HX1K) on Debian Linux, both on i686 bare metal and amd64 platforms, the latter virtualized with VirtualBox 5.1.2 on MacOS X.

Several Open Source environments have emerged to help supporting programmable hardware. Those are not specific to the Lattice products and summarised here. Users of those tools are cordially invited to help bringing them to Debian.

Open Source Examples for the Lattice iCE HX1K and HX8K

In principle, any Verilog code should just work that

and such examples can be found throughout the net as indicated on the parental FPGA page. There are however device-specific hurdles, and for beginners, about everything is a hurdle, no matter what the device is. Please also look at

and there is

For a quick success follow the example below.

Example: Rotating LED Illumination

The Physical Constraints file (.pcf) describes the mapping between pin numbers and ports of the Verilog module. It consist of multiple lines of "set_io D1 99", where D1 in this case is an input or output of the Verilog module called "D1", and 99 is the pin number of the Lattice FPGA.

Example .pcf file (which works with HX1K):

set_io D1 99
set_io D2 98
set_io D3 97
set_io D4 96
set_io D5 95
set_io clk 21

For specifications of all the ports of the HX1K iCEstick boards and their mapping to the chip, see the user manual download able from .

Verilog (.v) example

The file is borrowed from the arachne-pnr/examples directory. Per se it is independent from the FPGA. Yosys determines the chip type and it is only with the arachne-pnr that the association with the physical constraints file is manifested in the code so it is working on a particular soldering configuration since it is mostly arbitrary which ports are linked up with the LEDs.

   1 module top(input clk, output D1, output D2, output D3, output D4, output D5);
   3    reg ready = 0;
   4    reg [23:0]     divider;
   5    reg [3:0]      rot;
   7    always @(posedge clk) begin
   8       if (ready) 
   9     begin
  10        if (divider == 12000000) 
  11          begin
  12         divider <= 0;
  13     //  rot <= {rot[2:0],rot[3]}; // clockwise
  14         rot <= {rot[0],rot[3:1]}; // counter-clockwise
  15          end
  16        else 
  17          divider <= divider + 1;
  18     end 
  19       else 
  20     begin
  21        ready <= 1;
  22        rot <= 4'b0001;
  23        divider <= 0;
  24     end 
  25    end 
  27    assign D1 = rot[0];
  28    assign D2 = rot[1];
  29    assign D3 = rot[2];
  30    assign D4 = rot[3];
  31    assign D5 = 1;
  32 endmodule

The outputs are directed by the .pcf file to the LED lights. The rotation of that bit in 'rot' indeed turns the light counter clockwise. So, if you had a fabric new iCE stick that already shows a rotating light by default once it is provided with power, the device just changed the direction.