Translation(s): none
Theory
Makefiles support some different structures that you can use in your projects:
- Comments : Comments are any text beginning with the pound (#) sign. The comment can start anywhere on a line, even after other commands, and will continue until the end of the line.
- Variables : Make has a simple macro definition and substitution mechanism. There are lots of default macros. To find out what rules/macros make is using type: make -p
- Rules : The general syntax of a Makefile Target Rule is
- target [target...] : [dependent ....]
- [ command ...]
- Continuation of Lines : If you finish a line with the symbol "\", the program will understand that the next line is a continuation of this. It is very useful to be able to visually split long macros and/or rules.
- Special Macros : There are certain special macros predefined:
- $@ is the name of the file to be made
- $? is the names of the changed dependents
$< the name of the related file that caused the action
- $* the prefix shared by target and dependent files
- Implicit Rules : A rule is implicit when no particular target is mentioned:
- A command that, for example, ought to work in all cases where we build an executable x out of the source code x.c can be stated as an implicit rule:
- .c:
- $(CC) $(CFLAGS) $@.c $(LDFLAGS) -o $@
- Another common implicit rule is for the construction of .o (object) files out of .c (source files).
- .o.c:
$(CC) $(CFLAGS) -c $<
- alternatively
- .o.c:
- $(CC) $(CFLAGS) -c $*.c
- A command that, for example, ought to work in all cases where we build an executable x out of the source code x.c can be stated as an implicit rule: