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Theory

make is an utility for automatically building applications. The files specifying the instructions needed for that are usually named "Makefile". make tracks which files have changed since the last time the project was built, and invokes the compiler on only those source code files and their dependencies.

A rule (or target) tells Make both when and how to make a file. The general syntax of a Makefile rule is:

The commands inside each target must be indented by a tabulator, not by spaces. If you ever forget about that, and try to use spaces instead, you'll get an error message.

The make process is recursive, so it'll take care that all the dependences are fulfilled before trying to generate the target, and in case they did not exist, or if any its dependencies are newer than their own timestamps, the rule for generating them will be called first.

The syntax of the command make is: make [ -f makefile ] [ options ] ... [ targets ] ...

When you call the make program, you can select which target you want make to generate. If you don't say any, make will pick the first one automatically for you.

The most important options you'll have to know for using make are:

Exercises

We're developing a simple Makefile to build the test program we have already made:

$ cat >Makefile

To build the program now, we'll only have to execute:

$ make

$ make

You can have a more elaborated Makefile that allows you to select the compilation and linking options when make is invoked, and it's also quite usual to add a clean target to remove the files generated by make. Lets go to it:

$ cat >Makefile

Lets test it:

$ make clean

$ make

$ make clean

$ make CFLAGS="-Wall -O2"